The present invention relates to MIS-semiconductor-device fabrication methods for attaining further reduced dimension while enabling high-speed operation with low power consumption.
As the number of devices included in a semiconductor integrated circuit continues to increase, MIS transistors are required to be further decreased in size. To achieve such downsizing, MIS transistors need to have a heavily doped channel structure in which the channel region has a high impurity concentration.
A conventional method for fabricating an MIS transistor will be described with reference to the accompanying drawings.
FIGS. 5A through 5C and FIGS. 6A and 6B are cross-sectional views illustrating process steps in the conventional method for fabricating an MIS transistor.
First, ions of indium (In) as a p-type impurity are implanted into a semiconductor substrate 101 of p-type silicon at an acceleration voltage of 100 keV and at a dose of approximately 1xc3x971014/cm2. After the ion implantation process has been performed, an annealing process is carried out, thereby forming a p-type doped channel layer 102 in a channel-formation region in the semiconductor substrate 101 as shown in FIG. 5A.
Next, as shown in FIG. 5B, a gate oxide film 103 with a thickness of about 1.5 nm is formed on the semiconductor substrate 101, and a gate electrode 104 of polysilicon with a thickness of about 100 nm is formed on the gate oxide film 103.
Next, as shown in FIG. 5C, with the gate electrode 104 used as a mask, ions of arsenic (As) as an n-type impurity are implanted into the semiconductor substrate 101 at an acceleration voltage of 2 keV and at a dose of about 5xc3x971014/cm2, thereby forming n-type implantation layers 105A. Then, with the gate electrode 104 used as a mask, ions of boron (B) as a p-type impurity are implanted into the semiconductor substrate 101 at an acceleration voltage of 5 keV and at a dose of approximately 2xc3x971013/cm2, thereby forming p-type implantation layers 106A.
Thereafter, as shown in FIG. 6A, an insulating film of silicon nitride or silicon oxide is deposited to a thickness of approximately 50 nm on the semiconductor substrate 101. The deposited insulating film is then subjected to an anisotropic etching process, thereby forming sidewalls 107 on the lateral faces of the gate electrode 104.
Subsequently, with the gate electrode 104 and the sidewalls 107 as shown in FIG. 6B used as a mask, ions of arsenic as an n-type impurity are implanted into the semiconductor substrate 101 at an acceleration voltage of 15 keV and at a dose of approximately 3xc3x971015/cm2. The semiconductor substrate 101 is then subjected to a high-temperature, short-term annealing process. In this manner, n-type doped source/drain layers 108 are defined in regions in the semiconductor substrate 101 laterally with respect to each sidewall 107. At the same time, the ions existing in the n-type implantation layers 105A are diffused, whereby n-type doped extension layers 105B are defined in regions in the semiconductor substrate 101 between the n-type doped source/drain layers 108 and the p-type doped channel layer 102. And the ions existing in the p-type implantation layers 106A are diffused, whereby p-type doped pocket layers 106B are defined in regions in the semiconductor substrate 101 underneath the n-type doped extension layers 105B.
As described above, in the conventional MIS transistor-fabrication method, in order to attain transistor downsizing without making the short channel effects become evident, indium ions, which are heavy ions having a larger mass number than that of boron (B) ions, are used as impurity ions to form the p-type doped channel layer 102 and furthermore, the indium ion implantation dose is likely to be made larger.
However, implanting indium ions at a high dose into the semiconductor substrate 101 causes the ion-implanted region of the semiconductor substrate 101 to become amorphous. Thus, when the subsequent annealing process is carried out to activate the ions implanted, an EOR (end-of-range) dislocation-loop defect layer (hereinafter referred to simply as xe2x80x9cdislocation-loop defect layerxe2x80x9d) forms in the lower vicinity of the interface between the amorphous layer and the crystal layer, and the indium is strongly segregates to the dislocation-loop defect layer. As a result, the activated concentration decreases in the p-type doped channel layer 102, such that a desired impurity profile cannot be obtained.
The formation of the dislocation-loop defect layer in the p-type doped channel layer 102 also causes a leakage current to flow along the dislocation-loop defect layer.
FIG. 7 is a graph showing an impurity profile in the p-type doped channel layer 102 for the cross section taken along the line Axe2x80x94A shown in FIG. 5A. In FIG. 7, the abscissa represents the depth from the substrate surface while the ordinate represents the concentration of the indium ions logarithmically. As can be seen from FIG. 7, distribution of the indium contained in the p-type doped channel layer 102 segregates to the dislocation-loop defect layer formed near the amorphous-crystal interface due to the annealing process.
Accordingly, with the conventional semiconductor-fabrication method, the formation, indispensable for transistor downsizing, of heavily doped channel layers such that they have desired impurity concentration is difficult.
In view of the above problems, an object of the present invention is to ensure high impurity concentration in a doped channel layer while controlling manifestation of the short channel effects that accompany downsizing, and at the same time to control increases in a leakage current caused by a low threshold voltage and by the high-impurity-concentration channel.
To achieve the above object, according to a semiconductor fabrication method of the present invention, heavy ions are implanted multiple times, as impurity ions for forming a channel, at such a dose as not to cause a dislocation-loop defect layer to form, and an annealing process is performed after every time the ions have been implanted, whereby a heavily doped channel layer having a steep retro-grade impurity profile can be obtained.
Specifically, an inventive method for fabricating a semiconductor device includes the steps of (a) implanting ions of a first impurity of a first conductivity type, which are heavy ions having a relatively large mass number, multiple times into a channel-formation region in a semiconductor substrate at a dose such that the channel-formation region is not caused to become amorphous, and carrying out a first annealing process after each of the ion implantations has been performed, thereby removing the implantation damage in the channel-formation region and at the same time forming a first doped layer of the first conductivity type in the channel-formation region; (b) forming a gate insulating film on the semiconductor substrate, and selectively forming a gate electrode on the gate insulating film; (c) implanting ions of a second impurity of a second conductivity type into the semiconductor substrate with the gate electrode used as a mask; and (d) subjecting the semiconductor substrate to a second annealing process to diffuse the ions of the second impurity, thereby forming a second doped layer of the second conductivity type having a relatively shallow junction site.
According to the inventive method, no dislocation-loop defect layer is formed in the channel-formation region through the first annealing process that is carried out after the heavy ions have been implanted. It is therefore possible to prevent the heavy ions implanted into the channel-formation region from segregating to the dislocation-loop defect layer and being deactivated. Leakage current caused by the dislocation-loop defect layer can also be prevented since no dislocation-loop defect layer is formed.
Additionally, since the heavy ions are implanted multiple times at a low dose, the impurity concentration of the channel-formation region is not deficient. Moreover, the heavy ions are implanted at a dose such that no amorphization is caused and the annealing process is performed after each implantation has been carried out, which can restore the semiconductor crystal from post-implantation damage that each heavy-ion implantation instance causes. Accordingly, it can be ensured that a doped channel layer having a predetermined high impurity concentration is realized by using heavy ions.
In the step (d) of the inventive method, a dislocation-loop defect layer may be formed in the second doped layer in the semiconductor substrate, and by segregation of the ions of the first impurity to the dislocation-loop defect layer, a third doped layer of the first conductivity type may be formed in a region under the second doped layer.
Then, it is not necessary to form a doped pocket layer, which is made of the third doped layer whose conductivity type is different from that of the second doped layer, under a doped extension layer, which is made of the second doped layer. This results in suppressing the short channel effect further.
Alternatively, the inventive method may further include, between the steps (b) and (d), the steps of: implanting ions of a third impurity of the first conductivity type into the semiconductor substrate with the gate electrode used as a mask; and through the second annealing process, diffusing the ions of the third impurity to form a third doped layer of the first conductivity type under the second doped layer.
Then, it can be ensured that a doped pocket layer, which is made of the third doped layer, is formed.
The inventive method preferably further includes, the steps of, after the step (d) has been performed: forming a sidewall out of an insulating film on a lateral face of the gate electrode; and implanting ions of a fourth impurity of the second conductivity type into the semiconductor substrate with the gate electrode and the sidewall used as a mask, and then performing a third annealing process to diffuse the ions of the fourth impurity, thereby forming, outward of the second doped layer, a fourth doped layer of the second conductivity type, the forth doped layer having a deeper junction than the second doped layer.
In the inventive method, the heavy ions are preferably implanted at a dose not more than approximately 5xc3x971013/cm2.
In the inventive method, the first annealing process is preferably a rapid thermal annealing process in which the annealing temperature is increased to a peak temperature of about 850xc2x0 C. through 1050xc2x0 C. at a rate not less than about 100xc2x0 C./sec. and then the peak temperature is either maintained for about ten seconds at longest, or not maintained.
In the inventive method, the heavy ions are preferably indium ions.